Activity: Talk or presentation › Invited talk at conference or symposium › Science to science
System Efficient ESD Design (SEED) address the protection of I/O against ESD using simulation. This allows to predict the robustness against damaging ESD and allows to reduce the likelihood of disturbances caused by ESD (soft-failure). Reduced design margin due to smaller, less current carrying metallization and contacts and thinner gate oxide has reduced the design window for ESD protection to a few V and currents of less than 2 A for high speed I/O such as USB 4.x. This, and the need to use low capacitance devices (less than 0.2 pF) inhibits a design by data sheet. In simulation based design models for the TVS, which include the transient turn-on and models for the IO of the IC are combined with all passive interconnect to create a model that predicts currents and voltage at the IC for different rise time and amplitude ESD pulses.