Sparse matrix assembly on the GPU through multiplication patterns

R. Zayer, M. Steinberger, H. P. Seidel

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandBegutachtung


The numerical treatment of variational problems gives rise to large sparse matrices, which are typically assembled by coalescing elementary contributions. As the explicit matrix form is required by numerical solvers, the assembly step can be a potential bottleneck, especially in implicit and time dependent settings where considerable updates are needed. On standard HPC platforms, this process can be vectorized by taking advantage of additional mesh querying data structures. However, on graphics hardware, vectorization is inhibited by limited memory resources. In this paper, we propose a lean unstructured mesh representation, which allows casting the assembly problem as a sparse matrix-matrix multiplication. We demonstrate how the global graph connectivity of the assembled matrix can be captured through basic linear algebra operations and show how local interactions between nodes/degrees of freedom within an element can be encoded by means of concise representation, action maps. These ideas not only reduce the memory storage requirements but also cut down on the bulk of data that needs to be moved from global storage to the compute units, which is crucial on parallel computing hardware, and in particular on the GPU. Furthermore, we analyze the effect of mesh memory layout on the assembly performance.
Titel2017 IEEE High Performance Extreme Computing Conference (HPEC)
PublikationsstatusVeröffentlicht - 1 Sep 2017
Veranstaltung2017 IEEE High Performance Extreme Computing Conference: HPEC 2017 - Westin Hotel, Waltham, USA / Vereinigte Staaten
Dauer: 12 Sep 201714 Sep 2017


Konferenz2017 IEEE High Performance Extreme Computing Conference
KurztitelHPEC ‘17
Land/GebietUSA / Vereinigte Staaten


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