Solving the Discrete Logarithm of a 113-bit Koblitz Curve with an FPGA Cluster

Suchergebnisse

• Laufend

  A-SIT - Zentrum für sichere Informationstechnologie Austria

  Stranacher, K., Dominikus, S., Leitold, H., Marsalek, A., Teufl, P., Bauer, W., Aigner, M. J., Rössler, T., Neuherz, E., Dietrich, K., Zefferer, T., Mangard, S., Payer, U., Orthacker, C., Lipp, P., Reiter, A., Knall, T., Bratko, H., Bonato, M., Suzic, B., Zwattendorfer, B., Kreuzhuber, S., Oswald, M. E., Tauber, A., Posch, R., Bratko, D., Feichtner, J., Ivkovic, M., Reimair, F., Wolkerstorfer, J. & Scheibelhofer, K.

  21/05/99 → 6/08/20

  Projekt: Arbeitsgebiet

  • Cryptocurrency 100%
  • User 88%
  • Data Access 88%
  • Access Control 77%
  • Attribute-Based Encryption 66%
• Abgeschlossen

  Matthew - [Original in Englisch: Multi-entity-security using active Transmission Technology for improved Handling of Exportable security credentials Without privacy restrictions (MATTHEW Project)]

  Hanser, C., Wenger, E., Korak, T., Groß, H., Mangard, S. & Unterluggauer, T.

  1/11/13 → 31/10/16

  Projekt: Forschungsprojekt

  • Mobile Platform 100%
  • Usage Statistic 100%
  • Prefetch 100%
  • Systems and Application 50%
  • Gigabit Ethernet 50%

• NewP@ass - New verification & valdidation methods enabling widespread use of Privacy and @nonymity in electronically secured systems

  Röck, F., Unterluggauer, T., Könighofer, R., Mangard, S., Wenger, E., Spreitzer, R. C., Mendel, F., Schmidt, J. & Bloem, R.

  1/05/12 → 31/05/15

  Projekt: Forschungsprojekt

  • Security Component 100%
  • Operating Systems 100%
  • Security and Privacy 100%
  • Hardware Platform 100%
  • Engineering Process 100%

• IMPA Lab

  Posch, R., Rijmen, V., Posch, K., Kirschbaum, M., Schmidt, J., Schläffer, M., Szekely, A., Medwed, M., Plos, T., Peßl, P., Aigner, M. J., Wenger, E., Dominikus, S., Feldhofer, M., Hutter, M. & Oswald, M. E.

  1/10/99 → 15/07/19

  Projekt: Arbeitsgebiet

  • Attack 100%
  • Personal Identification Number 50%
  • Area 16%
  • side-channel 16%
  • User Privacy 10%

• VLSI Design

  Medwed, M., Wenger, E., Aigner, M. J., Posch, K., Hutter, M., Kirschbaum, M., Schmidt, J., Posch, R., Dominikus, S., Szekely, A., Feldhofer, M. & Plos, T.

  1/01/95 → 15/07/19

  Projekt: Arbeitsgebiet

  • Hardware Architecture 100%
  • Standards 66%
  • Throughput 66%
  • Hardware Designer 33%
  • Gate Equivalent 33%