Proving SIFA Protection of Masked Redundant Circuits

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Abstract

Implementation attacks like side-channel and fault attacks pose a considerable threat to cryptographic devices that are physically accessible by an attacker. As a consequence, devices like smart cards implement corresponding countermeasures like redundant computation and masking. Recently, statistically ineffective fault attacks (SIFA) were shown to be able to circumvent these classical countermeasure techniques. We present a new approach for verifying the SIFA protection of arbitrary masked implementations in both hardware and software. The proposed method uses Boolean dependency analysis, factorization, and known properties of masked computations to show whether the fault detection mechanism of redundant masked circuits can leak information about the processed secret values. We implemented this new method in a tool called Danira, which can show the SIFA resistance of cryptographic implementations like AES S-Boxes within minutes.
Originalspracheenglisch
TitelAutomated Technology for Verification and Analysis
Untertitel19th International Symposium, ATVA 2021
Herausgeber (Verlag)Springer
Seitenumfang16
PublikationsstatusAngenommen/In Druck - 2021
Veranstaltung19th International Symposium on Automated Technology for Verification and Analysis - Virtuell, Australien
Dauer: 18 Okt 202122 Okt 2021

Konferenz

Konferenz19th International Symposium on Automated Technology for Verification and Analysis
KurztitelATVA'21
LandAustralien
OrtVirtuell
Zeitraum18/10/2122/10/21

ASJC Scopus subject areas

  • !!Hardware and Architecture
  • !!Computer Science (miscellaneous)

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