Protecting RISC-V Processors against Physical Attacks

Mario Werner, Robert Schilling, Thomas Unterluggauer, Stefan Mangard

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem Konferenzband

Abstract

RISC-V is an emerging instruction-set architecture suitable for a wide variety of applications, which ranges from simple microcontrollers to high-performance CPUs. As an increasing number of commercial vendors now plans to adopt the architecture in their products, its security aspects are becoming a significant concern. For microcontroller implementations of RISC-V, one of the main security risks are attackers with direct physical access to the microchip. These physical attackers can perform highly powerful attacks that span from memory probing to power analysis up to fault injection and analysis. In this paper, we give an overview of the capabilities of attackers with direct physical device access, common threat models and attack vectors, and possible countermeasures. Besides, we discuss in more detail current approaches to secure RISC-V processors against fault injection attacks on the microchip itself. First, we show how to protect the control-flow against fault attacks by using an encrypted instruction stream and decrypting it on-the-fly in a newly added pipeline stage between the processor's fetch and decode unit. Second, we show how to protect conditional branches against fault injection by adding redundancy to the comparison operation and entangling the comparison result with the encrypted instruction stream. Finally, we discuss an approach to protect all pointers and memory accesses from tampering.
Originalspracheenglisch
TitelDesign, Automation & Test in Europe Conference - DATE 2019
Seiten1136-1141
Seitenumfang6
ISBN (elektronisch) 978-3-9819263-2-3
DOIs
PublikationsstatusVeröffentlicht - 2019
Veranstaltung2019 Design, Automation & Test in Europe Conference & Exhibition - Firenze, Italien
Dauer: 25 Mär 201929 Mär 2019

Konferenz

Konferenz2019 Design, Automation & Test in Europe Conference & Exhibition
KurztitelDATE 2019
LandItalien
OrtFirenze
Zeitraum25/03/1929/03/19

Schlagwörter

  • RISC-V
  • physical attacks
  • fault injection
  • countermeasures

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