Abstract
Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.
Originalsprache | englisch |
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Titel | 2021 58th ACM/IEEE Design Automation Conference (DAC) |
Seiten | 1285-1290 |
DOIs | |
Publikationsstatus | Veröffentlicht - 2021 |
Veranstaltung | 58th Design Automation Conference - San Francisco, USA / Vereinigte Staaten Dauer: 5 Dez. 2021 → 9 Dez. 2021 |
Konferenz
Konferenz | 58th Design Automation Conference |
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Kurztitel | DAC 2021 |
Land/Gebiet | USA / Vereinigte Staaten |
Ort | San Francisco |
Zeitraum | 5/12/21 → 9/12/21 |