Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber

Sujoy Sinha Roy, Andrea Basso

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem Konferenzband

Abstract

Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.
Originalspracheenglisch
TitelDesign Automation Conference (DAC 2021)
Seitenumfang6
PublikationsstatusEingereicht - Dez 2021
Veranstaltung58th Design Automation Conference - San Francisco, USA / Vereinigte Staaten
Dauer: 5 Dez 20219 Dez 2021

Konferenz

Konferenz58th Design Automation Conference
KurztitelDAC 2021
LandUSA / Vereinigte Staaten
OrtSan Francisco
Zeitraum5/12/219/12/21

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