Multi-dimensional optimization of charge preamplifier in 0.18 μm CMOS technology for low Power CdTe spectro-imaging system

Presented work is dedicated to research on pixelated CdTe spectro-imaging systems for space applications. The current study is focused on charge amplifier optimization for low dark current (less than 5 pA) and low input capacitance (0.3 to 1 pF) detector front-end. High spatial resolution and minimized power consumption are the most important parameters. Previous studies considered pixel size of approximately 600 μm. With technological advance of packaging systems and CdTe development, the pixel size of the detector and stray capacitance between pixel and electronics can be reduced. Consequently the dark current and the input capacitance will decrease. Our goal is to optimize the electronics readout for the small pixel detector system to approach as close as possible to the physical limits of the CdTe detector spectral resolution. In this article studies on 0.18 μm CMOS technology for a very low power conversion chain are presented.