Abstract
Reliability testing of Si power semiconductors has had a long history and has resulted in a good predictability of standard degradation-mechanism tests such as power cycling. To enable a rapid adoption of SiC MOSFETs into the mass market, application stress tests have also been carried out. In order to validate robustness, and assess end-of-life behavior, it is necessary to monitor performance-relevant device parameters throughout the tests. Application stress tests, however, are notorious for imposing limitations on the type of measurements that can be integrated into the test. Here, a modular system for parallel application stress tests is presented. This work also investigates how well one can carry out characterization measurements directly on the application test board. A discussion on the challenges and reasons for the selected solution are presented. The last part of this article presents the results of a bias-temperature instability investigation to demonstrate the feasibility of the proposed solution.
Originalsprache | englisch |
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Aufsatznummer | 113731 |
Seitenumfang | 6 |
Fachzeitschrift | Microelectronics Reliability |
Jahrgang | 114 |
DOIs | |
Publikationsstatus | Veröffentlicht - Nov. 2020 |
ASJC Scopus subject areas
- Elektronische, optische und magnetische Materialien
- Atom- und Molekularphysik sowie Optik
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Physik der kondensierten Materie
- Oberflächen, Beschichtungen und Folien
- Elektrotechnik und Elektronik
Fields of Expertise
- Information, Communication & Computing