Modular Test System Architecture for Device, Circuit and System Level Reliability Testing

Roland Sleik, Michael Glavanovics, Sascha Einspieler, Annette Mütze, Klaus Krischan

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandForschungBegutachtung

Originalspracheenglisch
TitelIEEE Applied Power Electronics Conference and Exposition
Herausgeber (Verlag).
Seiten1-7
PublikationsstatusVeröffentlicht - 2016
VeranstaltungIEEE Applied Power Electronics Conference and Exposition - Long Beach, CA, USA / Vereinigte Staaten
Dauer: 20 Mär 201624 Mär 2016

Konferenz

KonferenzIEEE Applied Power Electronics Conference and Exposition
LandUSA / Vereinigte Staaten
OrtLong Beach, CA
Zeitraum20/03/1624/03/16

Fields of Expertise

  • Sonstiges

Treatment code (Nähere Zuordnung)

  • Application

Dies zitieren

Sleik, R., Glavanovics, M., Einspieler, S., Mütze, A., & Krischan, K. (2016). Modular Test System Architecture for Device, Circuit and System Level Reliability Testing. in IEEE Applied Power Electronics Conference and Exposition (S. 1-7). ..

Modular Test System Architecture for Device, Circuit and System Level Reliability Testing. / Sleik, Roland; Glavanovics, Michael; Einspieler, Sascha; Mütze, Annette; Krischan, Klaus.

IEEE Applied Power Electronics Conference and Exposition. ., 2016. S. 1-7.

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandForschungBegutachtung

Sleik, R, Glavanovics, M, Einspieler, S, Mütze, A & Krischan, K 2016, Modular Test System Architecture for Device, Circuit and System Level Reliability Testing. in IEEE Applied Power Electronics Conference and Exposition. ., S. 1-7, Long Beach, CA, USA / Vereinigte Staaten, 20/03/16.
Sleik R, Glavanovics M, Einspieler S, Mütze A, Krischan K. Modular Test System Architecture for Device, Circuit and System Level Reliability Testing. in IEEE Applied Power Electronics Conference and Exposition. . 2016. S. 1-7
Sleik, Roland ; Glavanovics, Michael ; Einspieler, Sascha ; Mütze, Annette ; Krischan, Klaus. / Modular Test System Architecture for Device, Circuit and System Level Reliability Testing. IEEE Applied Power Electronics Conference and Exposition. ., 2016. S. 1-7
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