Projekte pro Jahr
Abstract
Homomorphic encryption enables computation on encrypted data, and hence it has a great potential in privacypreserving outsourcing of computations to the cloud. Hardware acceleration of homomorphic encryption is crucial as software implementations are very slow. In this paper, we present design methodologies for building a programmable hardware accelerator for speeding up the cloudside homomorphic evaluations on encrypted data.
First, we propose a divideandconquer technique that enables homomorphic evaluations in the polynomial ring $R_{Q,2N} = \mathbb{Z}_{Q}[x]/(x^{2N} + 1)$ to use a hardware accelerator that has been built for the smaller ring $R_{Q,N} = \mathbb{Z}_{Q}[x]/(x^{N} + 1)$. The technique makes it possible to use a single hardware accelerator flexibly for supporting several homomorphic encryption parameter sets.
Next, we present several architectural design methods that we use to realize the flexible and instructionset accelerator architecture, which we call `Medha'. At every level of the implementation hierarchy, we explore possibilities for parallel processing. Starting from hardwarefriendly parallel algorithms for the basic building blocks, we gradually build heavily parallel RNS polynomial arithmetic units. Next, many of these parallel units are interconnected elegantly so that their interconnections require the minimum number of nets, therefore making the overall architecture placementfriendly on the platform. As homomorphic encryption is computation as well as datacentric, the speed of homomorphic evaluations depends greatly on the way the data variables are handled. For Medha, we take a memoryconservative design approach and get rid of any offchip memory access during homomorphic evaluations.
Finally, we implement Medha in a Xilinx Alveo U250 FPGA and measure timing performances of the microcoded homomorphic addition, multiplication, keyswitching, and rescaling routines for the leveled fully homomorphic encryption scheme RNSHEAAN at 200 MHz clock frequency. For the large parameter sets $(\log Q, N) = (438, 2^{14})$ and $(546, 2^{15})$, Medha achieves accelerations by up to $68\times$ and $78\times$ times respectively compared to a highly optimized software implementation Microsoft SEAL running at 2.3 GHz.
First, we propose a divideandconquer technique that enables homomorphic evaluations in the polynomial ring $R_{Q,2N} = \mathbb{Z}_{Q}[x]/(x^{2N} + 1)$ to use a hardware accelerator that has been built for the smaller ring $R_{Q,N} = \mathbb{Z}_{Q}[x]/(x^{N} + 1)$. The technique makes it possible to use a single hardware accelerator flexibly for supporting several homomorphic encryption parameter sets.
Next, we present several architectural design methods that we use to realize the flexible and instructionset accelerator architecture, which we call `Medha'. At every level of the implementation hierarchy, we explore possibilities for parallel processing. Starting from hardwarefriendly parallel algorithms for the basic building blocks, we gradually build heavily parallel RNS polynomial arithmetic units. Next, many of these parallel units are interconnected elegantly so that their interconnections require the minimum number of nets, therefore making the overall architecture placementfriendly on the platform. As homomorphic encryption is computation as well as datacentric, the speed of homomorphic evaluations depends greatly on the way the data variables are handled. For Medha, we take a memoryconservative design approach and get rid of any offchip memory access during homomorphic evaluations.
Finally, we implement Medha in a Xilinx Alveo U250 FPGA and measure timing performances of the microcoded homomorphic addition, multiplication, keyswitching, and rescaling routines for the leveled fully homomorphic encryption scheme RNSHEAAN at 200 MHz clock frequency. For the large parameter sets $(\log Q, N) = (438, 2^{14})$ and $(546, 2^{15})$, Medha achieves accelerations by up to $68\times$ and $78\times$ times respectively compared to a highly optimized software implementation Microsoft SEAL running at 2.3 GHz.
Originalsprache  englisch 

Seitenumfang  38 
Fachzeitschrift  IACR Transactions on Cryptographic Hardware and Embedded Systems 
Jahrgang  2023 
Ausgabenummer  1 
Publikationsstatus  Angenommen/In Druck  2023 
Fingerprint
Untersuchen Sie die Forschungsthemen von „Medha: Microcoded Hardware Accelerator for computing on Encrypted Data“. Zusammen bilden sie einen einzigartigen Fingerprint.Projekte
 1 Abgeschlossen

HWHEANN  Beschleunigung des homomorphen RNSCKKSVerschlüsselungsschemas auf heterogenen CPUFPGAPlattformen
1/01/21 → 31/05/22
Projekt: Foschungsprojekt