Implementation Aspects of the DPA-Resistant Logic Style MDPL

Suchergebnisse

• Abgeschlossen

  EU - SCARD - Side Channel Analysis Resistant Design Flow

  Mangard, S., Herbst, C., Wolkerstorfer, J., Oswald, M. E., Popp, T., Tillich, S., Aigner, M. J. & Schmaranz, K.

  1/01/04 → 30/06/06

  Projekt: Forschungsprojekt

  • Channel Analysis 100%
  • side-channel 100%
  • Attack 75%
  • Power Analysis 50%
  • Threat 50%

• IMPA Lab

  Posch, R., Rijmen, V., Posch, K., Kirschbaum, M., Schmidt, J., Schläffer, M., Szekely, A., Medwed, M., Plos, T., Peßl, P., Aigner, M. J., Wenger, E., Dominikus, S., Feldhofer, M., Hutter, M. & Oswald, M. E.

  1/10/99 → 15/07/19

  Projekt: Arbeitsgebiet

  • Attack 100%
  • Personal Identification Number 50%
  • Area 16%
  • side-channel 16%
  • User Privacy 10%

• VLSI Design

  Medwed, M., Wenger, E., Aigner, M. J., Posch, K., Hutter, M., Kirschbaum, M., Schmidt, J., Posch, R., Dominikus, S., Szekely, A., Feldhofer, M. & Plos, T.

  1/01/95 → 15/07/19

  Projekt: Arbeitsgebiet

  • Hardware Architecture 100%
  • Standards 66%
  • Throughput 66%
  • Hardware Designer 33%
  • Gate Equivalent 33%