Gate extension area TID enhancement

Under influence of total ionizing dose (TID) MOS transistors change their electrical parameters. These effects can be enhanced or mitigated by physical realization of transistor. Reliability and matching in integrated circuits set specific layout requirements to MOS transistors. These requirements can include symmetrical gate contact placement and increased number of these contacts. Such layout may lead to increased area of polysilicon gate, extended over shallow trench isolation (STI). The major origin of TID effects in modern MOS transistors with thin gate oxide is charge trapping in STI and on its interface. The trapping process is highly dependent on weak electric field within this insulating layer. This electric field can be modified by the voltage applied to the gate overlapping STI regions. Within this work transistor gate extension area TID enhancement is discussed. Various custom designed MOS transistors with different gate extension areas are studied before and after irradiation with 60keV X-ray source. Experimental results are analysed and verified with the help of TCAD simulation.