ESD susceptibility characterization of an EUT by using 3D ESD scanning system

Kai Wang*, Jayong Koo, Giorgi Muchaidze, David J. Pommerenke

*Korrespondierende/r Autor/in für diese Arbeit

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem Konferenzband

Abstract

Electrostatic Discharges (ESD) can lead to soft-errors (e.g., bit-errors, wrong resets etc.) in digital electronics. The use of lower threshold voltages and faster I/O increases the sensitivity. In the analysis of ESD problems, an exact knowledge of the affected Pins and Nets is essential for an optimal solution. In this paper, a three dimensional ESD scanning system which has been developed to record the ESD susceptibility map for printed circuit board is presented and the mechanisms that the ESD event couples into the digital devices is studied The ESD susceptibility of a fast CMOS EUT is characterized by generating the susceptibility map of the EUT. A series of measurements of the noise coupled into a sensitive trace and pin during an ESD soft error event are presented.

Originalspracheenglisch
Titel2005 International Symposium on Electromagnetic Compatibility, EMC 2005
Seiten350-355
Seitenumfang6
DOIs
PublikationsstatusVeröffentlicht - 1 Dez 2005
Extern publiziertJa
Veranstaltung2005 International Symposium on Electromagnetic Compatibility: EMC 2005 - Chicago, USA / Vereinigte Staaten
Dauer: 8 Aug 200512 Aug 2005

Publikationsreihe

NameIEEE International Symposium on Electromagnetic Compatibility
Band2
ISSN (Print)1077-4076

Konferenz

Konferenz2005 International Symposium on Electromagnetic Compatibility
LandUSA / Vereinigte Staaten
OrtChicago
Zeitraum8/08/0512/08/05

ASJC Scopus subject areas

  • !!Condensed Matter Physics
  • !!Electrical and Electronic Engineering

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