ESD immunity prediction of D flip-flop in the ISO 10605 standard using a behavioral modeling methodology

Guangyao Shen*, Sen Yang, Victor V. Khilkevich, David J. Pommerenke, Hermann L. Aichele, Dirk R. Eichel, Christoph Keller

*Korrespondierende/r Autor/in für diese Arbeit

Publikation: Beitrag in einer FachzeitschriftArtikel

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18-MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup, including parallel and twisted pair harnesses, is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the failure level with the error of less than 20% in parallel harness case and around 30% in the twisted pair case.

Originalspracheenglisch
Aufsatznummer7089237
Seiten (von - bis)651-659
Seitenumfang9
FachzeitschriftIEEE Transactions on Electromagnetic Compatibility
Jahrgang57
Ausgabenummer4
DOIs
PublikationsstatusVeröffentlicht - 1 Aug 2015
Extern publiziertJa

ASJC Scopus subject areas

  • !!Atomic and Molecular Physics, and Optics
  • !!Condensed Matter Physics
  • !!Electrical and Electronic Engineering

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