An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order

Hannes Groß*, Stefan Mangard, Thomas Korak

*Korrespondierende/r Autor/-in für diese Arbeit

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandBegutachtung

Abstract

Passive physical attacks, like power analysis, pose a serious threat to the security of digital circuits. In this work, we introduce an efficient side-channel protected Advanced Encryption Standard (AES) hardware design that is completely scalable in terms of protection order. Therefore, we revisit the private circuits scheme of Ishai et al. [13] which is known to be vulnerable to glitches. We demonstrate how to achieve resistance against multivariate higher-order attacks in the presence of glitches for the same randomness cost as the private circuits scheme. Although our AES design is scalable, it is smaller, faster, and less randomness demanding than other side-channel protected AES implementations. Our first-order secure AES design, for example, requires only 18 bits of randomness per S-box operation and 6 kGE of chip area. We demonstrate the flexibility of our AES implementation by synthesizing it up to the 15th protection order.
Originalspracheenglisch
TitelTopics in Cryptology – CT-RSA 2017
ErscheinungsortCham
Herausgeber (Verlag)Springer
Seiten95-112
Seitenumfang18
ISBN (Print)978-3-319-52152-7
DOIs
PublikationsstatusVeröffentlicht - 2017
VeranstaltungTopics in Cryptology - The Cryptographer's Track at the RSA Conference 2017: CT-RSA 2017 - San Francisco, USA / Vereinigte Staaten
Dauer: 14 Feb. 201717 Feb. 2017
https://www.rambus.com/ct-rsa-2017/

Publikationsreihe

NameLecture Notes in Computer Science
Herausgeber (Verlag)Springer
Band10159

Konferenz

KonferenzTopics in Cryptology - The Cryptographer's Track at the RSA Conference 2017
KurztitelCT-RSA 2017
Land/GebietUSA / Vereinigte Staaten
OrtSan Francisco
Zeitraum14/02/1717/02/17
Internetadresse

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