A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange

Aikata Aikata, Ahmet Can Mert, Amitabh Das, Donald Matthews, Santosh Ghosh, Sujoy Sinha Roy

Publikation: Beitrag in einer FachzeitschriftArtikelBegutachtung

Abstract

We propose design methodologies for building a compact, unified and programmable cryptoprocessor architecture that computes post-quantum key agreement and digital signature. Synergies in the two types of cryptographic primitives are used to make the cryptoprocessor compact. As a case study, the cryptoprocessor architecture has been optimized targeting the signature scheme 'CRYSTALS-Dilithium' and the key encapsulation mechanism (KEM) 'Saber', both finalists in the NIST’s post-quantum cryptography standardization project. The programmable cryptoprocessor executes key generations, encapsulations, decapsulations, signature generations, and signature verifications for all the security levels of Dilithium and Saber. On a Xilinx Ultrascale+ FPGA, the proposed cryptoprocessor consumes 18,406 LUTs, 9,323 FFs, 4 DSPs, and 24 BRAMs. It achieves 200 MHz clock frequency and finishes CCA-secure key-generation/encapsulation/decapsulation operations for LightSaber in 29.6/40.4/ 58.3s; for Saber in 54.9/69.7/94.9s; and for FireSaber in 87.6/108.0/139.4s, respectively. It finishes key-generation/sign/verify operations for Dilithium-2 in 70.9/151.6/75.2s; for Dilithium-3 in 114.7/237/127.6s; and for Dilithium-5 in 194.2/342.1/228.9s, respectively, for the best-case scenario. On UMC 65nm library for ASIC the latency is improved by a factor of two due to a 2 increase in clock frequency.
Originalspracheenglisch
Seitenumfang13
FachzeitschriftIEEE Transactions on Computers
Jahrgang2022
Frühes Online-Datum10 Okt. 2022
DOIs
PublikationsstatusElektronische Veröffentlichung vor Drucklegung. - 10 Okt. 2022

ASJC Scopus subject areas

  • Software
  • Theoretische Informatik
  • Hardware und Architektur
  • Theoretische Informatik und Mathematik

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