In this paper, we present a methodology to characterize the I/O pins of a logic IC such as an application processor or ASIC with respect to soft-failure susceptibility due to electrostatic discharge. With the IC in a functional system, variable stress pulses are injected while the interface under test operates in real-world use cases. This test methodology enables the extraction of the IC behavior during ESD-like stress on a pin-by-pin basis. This characterization is intended to be performed during the validation stages of component development, making it possible to provide system developers with valuable information about potential modes of failure. This early detection of potential soft errors and their sensitivities can then be used to design for soft-failure robustness from the very beginning of system hardware and software design.
|Seiten (von - bis)||16-24|
|Fachzeitschrift||IEEE Transactions on Electromagnetic Compatibility|
|Publikationsstatus||Veröffentlicht - 1 Feb 2020|
ASJC Scopus subject areas
- !!Atomic and Molecular Physics, and Optics
- !!Condensed Matter Physics
- !!Electrical and Electronic Engineering