A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

Benjamin J. Orr*, Sebastian Koch, Harald Gossner, David J. Pommerenke

*Korrespondierende/r Autor/in für diese Arbeit

Publikation: Beitrag in einer FachzeitschriftArtikel

Abstract

In this paper, we present a methodology to characterize the I/O pins of a logic IC such as an application processor or ASIC with respect to soft-failure susceptibility due to electrostatic discharge. With the IC in a functional system, variable stress pulses are injected while the interface under test operates in real-world use cases. This test methodology enables the extraction of the IC behavior during ESD-like stress on a pin-by-pin basis. This characterization is intended to be performed during the validation stages of component development, making it possible to provide system developers with valuable information about potential modes of failure. This early detection of potential soft errors and their sensitivities can then be used to design for soft-failure robustness from the very beginning of system hardware and software design.

Originalspracheenglisch
Aufsatznummer8844106
Seiten (von - bis)16-24
Seitenumfang9
FachzeitschriftIEEE Transactions on Electromagnetic Compatibility
Jahrgang62
Ausgabenummer1
DOIs
PublikationsstatusVeröffentlicht - 1 Feb 2020
Extern publiziertJa

ASJC Scopus subject areas

  • !!Atomic and Molecular Physics, and Optics
  • !!Condensed Matter Physics
  • !!Electrical and Electronic Engineering

Fingerprint

Untersuchen Sie die Forschungsthemen von „A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge“. Zusammen bilden sie einen einzigartigen Fingerprint.

Dieses zitieren