A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Robert Kappel, Mario Auer, Wolfgang Pribyl, Guenter Hofer, Gerald Holweg

Publikation: KonferenzbeitragPaper

Abstract

In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.
Originalspracheenglisch
Seiten562-565
Seitenumfang4
PublikationsstatusVeröffentlicht - 2013
VeranstaltungIEEE International Symposium on Circuits and Systems: ISCAS 2013 - Beijing, China
Dauer: 19 Mai 201323 Mai 2013
http://ieee-cas.org/pubs/tcsvt/iscas-2013

Konferenz

KonferenzIEEE International Symposium on Circuits and Systems
LandChina
OrtBeijing
Zeitraum19/05/1323/05/13
Internetadresse

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