A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Robert Kappel, Mario Auer, Wolfgang Pribyl, Guenter Hofer, Gerald Holweg

Publikation: KonferenzbeitragPaperForschungBegutachtung

Abstract

In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.
Originalspracheenglisch
Seiten562-565
Seitenumfang4
PublikationsstatusVeröffentlicht - 2013
VeranstaltungInternational Symposium on Circuits and Systems (ISCAS) - Beijing, China
Dauer: 19 Mai 201323 Mai 2013
http://ieee-cas.org/pubs/tcsvt/iscas-2013

Konferenz

KonferenzInternational Symposium on Circuits and Systems (ISCAS)
LandChina
OrtBeijing
Zeitraum19/05/1323/05/13
Internetadresse

Fingerprint

Flip flop circuits
Fabrication
Electric potential
Compensation and Redress

Dies zitieren

Kappel, R., Auer, M., Pribyl, W., Hofer, G., & Holweg, G. (2013). A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV. 562-565. Beitrag in International Symposium on Circuits and Systems (ISCAS), Beijing, China.

A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV. / Kappel, Robert; Auer, Mario; Pribyl, Wolfgang; Hofer, Guenter; Holweg, Gerald.

2013. 562-565 Beitrag in International Symposium on Circuits and Systems (ISCAS), Beijing, China.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Kappel, R, Auer, M, Pribyl, W, Hofer, G & Holweg, G 2013, 'A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV' Beitrag in, Beijing, China, 19/05/13 - 23/05/13, S. 562-565.
Kappel R, Auer M, Pribyl W, Hofer G, Holweg G. A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV. 2013. Beitrag in International Symposium on Circuits and Systems (ISCAS), Beijing, China.
Kappel, Robert ; Auer, Mario ; Pribyl, Wolfgang ; Hofer, Guenter ; Holweg, Gerald. / A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV. Beitrag in International Symposium on Circuits and Systems (ISCAS), Beijing, China.4 S.
@conference{8c18342aecb84d33bea457ad8ef64ff9,
title = "A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV",
abstract = "In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89{\%} for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.",
author = "Robert Kappel and Mario Auer and Wolfgang Pribyl and Guenter Hofer and Gerald Holweg",
year = "2013",
language = "English",
pages = "562--565",
note = "International Symposium on Circuits and Systems (ISCAS) ; Conference date: 19-05-2013 Through 23-05-2013",
url = "http://ieee-cas.org/pubs/tcsvt/iscas-2013",

}

TY - CONF

T1 - A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

AU - Kappel, Robert

AU - Auer, Mario

AU - Pribyl, Wolfgang

AU - Hofer, Guenter

AU - Holweg, Gerald

PY - 2013

Y1 - 2013

N2 - In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

AB - In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

M3 - Paper

SP - 562

EP - 565

ER -