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Simulation-based verification is one of the most essential verification-methods in today's development of embedded systems. To ensure a reliable system, not only functional but also non-functional properties like timing, power, thermal or safety must be taken into account. These properties must also be verified concerning standards like the ISO26262 for functional safety in the automotive domain. Since millions of test kilometre have to be driven to ensure a reliable system, simulation is becoming more and more important, since the costs for physical tests cannot be handled anymore. One verification methods which has been established in the field of embedded systems is the Universal Verification Methodology (UVM). However, this method has the drawback of consuming too much time when executing thousands of simulations with varying parameters in a sequential manner. Therefore, it needs new methodologies to speed-up this verification process through parallelization. In this paper, we present a novel approach which extends the layered pattern of UVM with message patterns used in today's cloud computing. This helps design and verification engineers in the embedded system domain to gain their simulation results much faster. The result of this work is a complete verification environment, which uses the full potential of our newly defined verification pattern.
|Publikationsstatus||Veröffentlicht - 2016|
|Veranstaltung||21st European Conference on Pattern Languages of Programs: EuroPLoP 2016 - Kloster Irsee, Kaufbeuren, Deutschland|
Dauer: 6 Juli 2016 → 10 Juli 2016
|Konferenz||21st European Conference on Pattern Languages of Programs|
|Zeitraum||6/07/16 → 10/07/16|
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1/01/14 → 31/07/16