A Highly Regular and Scalable AES Hardware Architecture

Stefan Mangard, Manfred Aigner, Sandra Dominikus

Publikation: Beitrag in einer FachzeitschriftArtikelBegutachtung

Abstract

This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semicustom design flows. Contrary to other publications, a complete architecture (even including CBC mode) that is scalable in terms of throughput and in terms of the used key size is described. Similarities of encryption and decryption are utilized to provide a high level of performance using only a relatively small area (10,799 gate equivalents for the standard configuration). This performance is reached by balancing the combinational paths of the design. No other published AES hardware architecture provides similar balancing or a comparable regularity. Implementations of the fastest configuration of the architecture provide a throughput of 241 Mbits/sec on a 0.6 /spl mu/m CMOS process using standard cells.
Originalspracheenglisch
Seiten (von - bis)483-491
FachzeitschriftIEEE Transactions on Computers
Jahrgang52
Ausgabenummer4
DOIs
PublikationsstatusVeröffentlicht - 2003

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