A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits

Martin Unterweissacher

Publikation: StudienabschlussarbeitDissertationForschung

Originalsprachedeutsch
PublikationsstatusVeröffentlicht - 2009

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A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits. / Unterweissacher, Martin.

2009.

Publikation: StudienabschlussarbeitDissertationForschung

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year = "2009",
language = "deutsch",

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TY - THES

T1 - A Hierarchical Pre-Layout Power Integrity Simulation Flow for Mixed Signal & RF Integrated Circuits

AU - Unterweissacher, Martin

PY - 2009

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