A circuit model for ESD performance analysis of printed circuit boards

Byong Su Seol*, Jong Sung Lee, Jae Deok Lim, Hyungseok Lee, Harkbyeong Park, Argha Nandy, David Pommerenke

*Korrespondierende/r Autor/-in für diese Arbeit

Publikation: Beitrag in Buch/Bericht/KonferenzbandBeitrag in einem KonferenzbandBegutachtung

Abstract

This paper provides a SPICE-eompatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

Originalspracheenglisch
Titel2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings
Seiten120-123
Seitenumfang4
DOIs
PublikationsstatusVeröffentlicht - 1 Dez. 2008
Extern publiziertJa
Veranstaltung2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Seoul, Südkorea
Dauer: 10 Dez. 200812 Dez. 2008

Publikationsreihe

Name2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings

Konferenz

Konferenz2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008
Land/GebietSüdkorea
OrtSeoul
Zeitraum10/12/0812/12/08

ASJC Scopus subject areas

  • Steuerungs- und Systemtechnik
  • Elektrotechnik und Elektronik

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