VHDL - Fehlersuche in VHDL-Programmen

Projekt: Foschungsprojekt

Projektdetails

Beschreibung

Project 'Debugging VHDL Programs (DEV)' aims in supporting and if possible automating software debugging of VHDL programs. VHDL is a well-known hardware description language used during the design phase for describing the functionality of hardware devices, e.g., digital circuits (CPUs and ASICs). VHDL programs are usually large with up to 10 MB of source code and are written by a team of designers making locating and even correcting faults a time consuming task. Therefore using a debugger can reduce design costs and time to marked. The debugger to be developed during DEV adapts model-based diagnosis (MBD) for debugging. MBD had been developed for fixing faults in hardware and require the existence of a component oriented model describing the functionality of a system. Most technical systems have a component oriented view and this is also the case for software. Programs comprises several statements and expressions that can be viewed as components. The connections are then represented by variables and signals. This view on programs enables the use of the underlying theory and algorithms for MBD. However, it is not so easy to develop a general model to be used for debugging. Because the quality of the resulting model has an impact on the results, e.g., number of bug candidates, further research has to be done in this respect. Project DEV should therefore be a next step in providing program models in order to make the application of MBD to debugging more application oriented. DEV should provide the theoretical and practical base for developing a debugging tool for hardware designers. During DEV logical models of programs should be developed and practical requirements regarding debugging time, the user interface, and coupling debugging with simulation and verification tools, are to be considered. Project DEV is expected to deliver multiple models of programs for debugging, handling the models, empirically evaluate the results using real-world VHDL programs, improving diagnosis algorithms, and finally, using a planning system for controlling and optimizing the whole debugging process.
StatusAbschlussdatum
Tatsächlicher Beginn/ -es Ende1/11/0131/08/04

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