High-performance printed wire boards PWBs are abundant in our days and virtually constitute the area of modern electronic devices. The continuously growing demand to allocate complex circuits on incessantly decreasing dimensions (going nano) requires the availability of perfectly textured, smooth and consistent surfaces for the fabrication of continuously smaller PWBs from etching processes: The risk of over-/under-etching and the inherent failure rate by short circuits/wire breakages depend on the consistence of the initial surface and correlate reciprocally with the dimensions of the PWBs. Improving the consistence of a surface, by e.g. decreasing its roughness, however usually exponentially increases the manufacturing costs of the corresponding device.
The present project will continue and expand the precedent projects Polymers as matrix materials for integrated electronic materials (Kplus period with AT&S as partner company) and Generation of Smooth Surfaces (Intermediate funding period with Infineon AG Villach and AT&S as partner companies).
The herein proposed project will follow a bilateral strategy for the optimization/production of photo-resist coatings that ideally meet the requirements for devices with continuously decreasing feature size. The targeted interaction between analytical and synthetic approaches will be realizedby the establishment and verification of a theoretical model for the prediction of the adhesion of photo-resists to semiconductor materials. Moreover the compilation and application of a set of photo-resists for the coating of poly(imide)s and common FR4 basic materials (fibre glass reinforced epoxy resins), which are used in PWB industry, is aimed at.
The overall goals of these investigations are (i) a toolbox of photo-resists for the generation of tailor-made coatings and (ii) the delivery of a model for the finetuning of device properties from predictable process parameter alterations. Summing up, the optimization of current and future fabrication routines and the minimization of failure rates during the surface functionalization of semiconductors and printed wire boards is aimed at.