With the increasing demand on higher clock frequencies for synchronisation and data transmission, jitter has become the major limiting factor for today's high-speed clock and phase locked loop (PLL) based systems. In order to overcome these limitations an accurate description and quantification of jitter and its influences is required. We propose a concept study for on-chip diagnostic tools that efficiently quantify jitter and thus can be utilized in various monitoring and surveillance applications that help to reduce jitter influence and assist in verification of specification requirements for PLL systems. The concept study is based on a novel and promising analysis method, which efficiently decomposes jitter distributions in terms of the deterministic and random parts. This representation allows for a simple qualitative description of the performance of a PLL, and thus can be utilized by the industry in several important application fields, such as bit error rate (BER) estimation in data interfaces, jitter tolerance measurements and adaptive jitter optimization techniques in PLLs and clock systems. Therefore, the concept study will evaluate potential and limitations in each of these application fields and provide the required key specifications for a future bottom-up design of on-chip diagnostics and other related design-for-test structures. The developed concepts, block models and test benches can be utilized generically in a broad variety of applications for jitter timing analysis and related design verification. Combined with the powerful estimation principle, this will lead to significant performance improvements and novel on-chip diagnostic tools, and thus aid in handling timing jitter for future system designs.