By observing the runtime behavior of applications running on multiprocessor systems based on the digital signal processor TMS320C40, this monitor helps to tune the system performance. The monitor employs a novel hardware approach. By using of internal processor resources, the influence on the monitored application is minimal and an instrumentation of the application's source code is not necessary. For the design of the monitor, emphasis is placed on modularity and scalability. Thus, the monitor can be easily adapted to the user requirements and to the application size. The implementation of the monitor is comprised of several modules that are prototyped on FPGAs. They provide information like CPU workload, memory utilization and logical/physical interprocessor communication load. The monitor comprises also a graphical user interface including dynamic on-line visualizations of the measured data. Experiments showed the ability of the monitor to reflect the dynamic behavior of applications being measured.
|Tatsächlicher Beginn/ -es Ende||1/01/92 → 31/01/98|