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Forschungsoutput 1983 2019

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2019

A New Method for Measuring Parasitics of Super Junction Power MOSFETs

Fuchs, M., Spielberger, L., Sygulla, C. & Deutschmann, B., 3 Sep 2019.

Publikation: KonferenzbeitragPaperForschungBegutachtung

2018

Low TID effects on MOS transistors

Bezhenova, V., Michalowska-Forsyth, A. M. & Pflanzl, W., Sep 2018.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Modeling of annular gate MOS transistors

Bezhenova, V. & Michalowska-Forsyth, A. M., Sep 2018.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Prototype Design of a Magnetometer Frontend-ASIC for Spaceborne Applications

Auer, M., Scherzer, M., Valavanoglou, A., Leitner, S. & Magnes, W., 27 Sep 2018.

Publikation: KonferenzbeitragPaperForschungBegutachtung

2017
readout
detectors
counting
x rays
requirements

Pre-estimating the Electromagnetic Interference (EMI) of Electronic Systems

Auinger, B., Deutschmann, B., Winkler, G., Cecil, S. & Lamedschwandner, K., 27 Apr 2017, S. 15. 1 S.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Survey on Integrated High-Power Low-EmissionOutput Stages for Drivers of Low-FrequencyResonant Loads

Hackl, H., Auer, M. & Erckert, R., 2017, S. 64-69. 6 S.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Integrated circuits
Natural frequencies
Networks (circuits)
2016

Calculation of Very Near Field Radiated Emission of a Straight Cable Harness

Hackl, H. & Auinger, B., 27 Jun 2016.

Publikation: KonferenzbeitragPaperForschungBegutachtung

ESD protection characterization by an extended Wunsch-Bell plot

Schrey, P., 27 Jun 2016.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Electrostatic discharge
Electric power utilization
2013

A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Kappel, R., Auer, M., Pribyl, W., Hofer, G. & Holweg, G., 2013, S. 562-565. 4 S.

Publikation: KonferenzbeitragPaperForschungBegutachtung

Flip flop circuits
Fabrication
Electric potential
Compensation and Redress
2011

Switched Capacitor DC-DC Converter in 65nm CMOS Technology with a Peak Efficiency of 97%

Santa, T., Auer, M., Sandner, C. & Lindholm, C., 2011, S. 1351-1354. 4 S.

Publikation: KonferenzbeitragPaperForschungBegutachtung

DC-DC converters
Capacitors
Electric potential
Mobile devices
Switches